Conventional semiconductor manufacturing uses a number of processes to form semiconductor devices in substrates. The substrate can be a wafer, which is a small, thin, circular slice of a semiconducting material, such as silicon Semiconductor devices formed on the substrate may be discrete devices or integrated circuits. For example, the semiconductor devices may be composed of a single discrete power transistor, or may be formed from a number of transistors and other electronic elements, such as resistors, capacitors, etc., that are electrically coupled together to form an integrated circuit. After the formation of the semiconductor devices, the wafer is tested and diced to separate individual dies in the wafer.
As explained in U.S. patent application Ser. No. 11/189,163, by providing smaller dimensions in semiconductor devices and substrates, properties such as resistance, power dissipation, and parasitic impedance are reduced. In particular, thinning the silicon substrate after device fabrication reduces the on-resistance and the parasitic delay of modern low voltage rating DMOS and IGBT devices, respectively. In conventional semiconductor device fabrication processes, after the devices, other semiconductor layers, and metal layers have been formed, the substrate is often thinned by a process such as mechanical grinding or chemical mechanical polishing (CMP). Recent process developments have resulted in a final silicon substrate thinner than 100 μm.
However, there are a number of problems associated with processing the silicon substrate. For example, since the substrate is thin, it may warp or break at the stage of drain metallization, or at subsequent stages of wafer handling in a power MOSFET manufacturing process. The drain metallization process described in U.S. application Ser. No. 11/189,163 uses sputtering and evaporation During the stage of formation of the drain electrode, the stress and heat caused by conventional drain metallization methods such as sputtering or evaporation may lead to severe amounts of wafer warpage or breakage. And even if the wafers survive the drain formation process, ultra-thin wafers are susceptible to higher handling-related breakage.
Embodiments of the invention address the above problems and other problems individually and collectively.